As is known in this specific technical field, there exists a growing demand for both fast logic circuits and non-volatile memories to be integrated in a single electronic device. Filling this demand considerably complicates the fabrication process of such integrated electronic devices because, as explained hereinafter, the technologies involved in the fabrication of these types of circuits are not fully compatible. This leads to increased production costs and makes it more difficult to achieve high production rates.
For example, the fabrication of high-voltage (HV) transistors, as are required for handling high voltages (&gt;12V) at the programming stage of non-volatile memory cells, is complicated especially because it cannot be reconciled with the need to also provide low-voltage (LV) logic circuits with very fast MOS transistors.
In fact, high electric signal transmission speeds are usually achieved by using logic circuits comprised of transistors that have been subjected to a well-known silicidation process. This process consists essentially of metallizing with silicide, so to speak, the junctions of the transistors in the logic circuits, which is detrimental, however, to the junction breakdown performance.
This is at conflict with the need to provide high-voltage HV transistors having as a major characteristic thereof a higher resistance to breakdown.
In most fabrication processes with CMOS technology, the source and drain junctions of low-voltage MOS transistors are currently formed with a progressive profile by a double implantation of dopant known as LDD (Lightly Doped Drain).
Shown schematically in the attached FIG. 1, to an enlarged scale, is an exemplary structure of an N-channel MOS transistor 1 which has been formed by an LDD double implantation. A first implantation is lighter and allows a first region 3 to be formed self-aligned to the gate region 2; the second implantation is heavier and allows a second region 4 to be formed which is self-aligned to the so-called spacers 5 which isolate the gate region 2 laterally on opposite sides thereof. The spacers 5 are essentially dielectric material gussets located at the gate region 2 sides. Additionally to their isolation function, they allow the heavy junction implant to be spaced away from the gate edge.
The structure of a P-channel transistor is similar and easily obtained by substituting p-type regions for the n-type regions throughout, and vice versa.
The way high-voltage HV transistors are currently fabricated will now be described. A so-called drain extension technique is used for the purpose which yields lightly doped junctions and, therefore, a high breakdown value.
During the source and drain heavy implantation step for the low-voltage transistors, the HV transistors are fully masked off. The heavy implant only affects contact regions, to ensure good contacting.
As previously mentioned, the transistors of fast logic circuits go through a process step where the junctions are silicized, for less parasitic resistances and, hence, improved speed performance. The silicidation process becomes difficult where the underlying silicon is low-level doped, and accordingly does not suit the formation of HV transistors with drain extensions. Thus, it is obviously necessary to avoid silicidation of the drain extension junctions.
Latest generation processes usually provide for the transistors to be formed with gate regions doped with the same dopant type as the channel region, this feature being referred to as "dual gate". For this purpose, the gate region must be left unprotected during the heavy source and drain implantations.
This feature also implies that the gate regions of the HV transistors with drain extensions cannot be masked, not even partially so, from the heavy source and drain implantations.
A viable prior solution consisted of protecting the high-voltage transistor junctions with the dielectric utilized for defining the spacers, using an appropriate mask to prevent etching through certain regions.
However, this solution is complicated because it requires that the mask be not even partially covering any of the dual gate transistor gate regions, lest the polysilicon layer of the transistors is incorrectly implanted. If the gate region is not correctly implanted even at its sides, the threshold voltage of the affected transistor will not be the proper value.